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quad-channel, digital isolators, enhanced system-level esd reliability ADUM3400/adum3401/adum3402 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features enhanced system-level esd performance per iec 61000-4-x low power operation 5 v operation 1.4 ma per channel maximum @ 0 mbps to 2 mbps 4.3 ma per channel maximum @ 10 mbps 34 ma per channel maximum @ 90 mbps 3 v operation 0.9 ma per channel maximum @ 0 mbps to 2 mbps 2.4 ma per channel maximum @ 10 mbps 20 ma per channel maximum @ 90 mbps bidirectional communication 3 v/5 v level translation high temperature operation: 105c high data rate: dc to 90 mbps (nrz) precise timing characteristics 2 ns maximum pulse-width distortion 2 ns maximum channel-to-channel matching high common-mode transient immunity: >25 kv/s output enable function 16-lead soic wide body, pb-free package safety and regulatory approvals ul recognition: 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity din en 60747-5-2 (vde 0884 part 2): 2003-01 din en 60950 (vde 0805): 2001-12; en 60950: 2000 v iorm = 560 v peak applications general-purpose multichannel isolation spi? interface/data converter isolation rs-232/rs-422/rs-485 transceivers industrial field bus isolation general description the adum340x 1 are 4-channel digital isolators based on analog devices i coupler? technology. combining high speed cmos and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices. i coupler devices remove the design difficulties commonly associated with optocouplers. typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple i coupler digital interfaces and stable performance characteristics. the need for external drivers and other discrete components is eliminated with these i coupler products. furthermore, i coupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. the adum340x isolators provide three independent isolation channels in a variety of channel configurations and data rates (see the ordering guide ). all models operate with the supply voltage on either side ranging from 2.7 v to 5.5 v, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. the adum340x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. in comparison to the adum140x isolators, the adum340x isolators contain various circuit and layout changes to provide increased capability relative to system-level iec 61000-4-x testing (esd/burst/surge). the precise capability in these tests for either the adum140x or adum340x products is strongly determined by the design and layout of the users board or module. for more information, see application note an-793, esd/latch-up considerations with i coupler isolation products . 1 protected by u.s. patents 5,952,849 and 6,873,065. other patents pending. functional block diagrams encode decode encode decode encode decode encode decode v dd1 gnd 1 v ia v ib v ic v id nc gnd 1 v dd2 gnd 2 v oa v ob v oc v od v e2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 05983-001 figure 1. ADUM3400 functional block diagram decode encode encode decode encode decode encode decode v dd1 gnd 1 v ia v ib v ic v od v e1 gnd 1 v dd2 gnd 2 v oa v ob v oc v id v e2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 05983-002 figure 2. adum3401 functional block diagram decode encode decode encode encode decode encode decode v dd1 gnd 1 v ia v ib v oc v od v e1 gnd 1 v dd2 gnd 2 v oa v ob v ic v id v e2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 05983-003 figure 3. adum3402 functional block diagram
ADUM3400/adum3401/adum3402 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagrams............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 electrical characteristics5 v operation................................ 3 electrical characteristics3 v operation................................ 6 electrical characteristicsmixed 5 v/3 v or 3 v/5 v operation....................................................................................... 8 package characteristics ............................................................. 12 regulatory information............................................................. 12 insulation and safety-related specifications.......................... 12 din en 60747-5-2 (vde 0884 part 2) insulation characteristics ............................................................................ 13 recommended operating conditions .................................... 13 absolute maximum ratings ......................................................... 14 esd caution................................................................................ 14 pin configurations and function descriptions ......................... 15 typical performance characteristics ........................................... 18 application information................................................................ 20 pc board layout ........................................................................ 20 system-level esd considerations and enhancements ........ 20 propagation delay-related parameters................................... 20 dc correctness and magnetic field immunity........................... 20 power consumption .................................................................. 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 3/06revision 0: initial version
ADUM3400/adum3401/adum3402 rev. 0 | page 3 of 24 specifications electrical characteristics5 v operation 1 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 5 v. table 1. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.57 0.83 ma output supply current per channel, quiescent i ddo (q) 0.29 0.35 ma ADUM3400, total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 2.9 3.5 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 1.2 1.9 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 9.0 11.6 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 3.0 5.5 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 72 100 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 19 36 ma 45 mhz logic signal freq. adum3401, total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 2.5 3.2 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 1.6 2.4 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 7.4 10.6 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 4.4 6.5 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 59 82 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 32 46 ma 45 mhz logic signal freq. adum3402, total supply current, four channels 2 dc to 2 mbps v dd1 or v dd2 supply current i dd1 (q) , i dd2 (q) 2.0 2.8 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 or v dd2 supply current i dd1 (10) , i dd2 (10) 6.0 7.5 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 or v dd2 supply current i dd1 (90) , i dd2 (90) 51 62 ma 45 mhz logic signal freq. for all models input currents i ia , i ib , i ic , i id , i e1 , i e2 ?10 +0.01 +10 a 0 v ia , v ib , v ic , v id v dd1 or v dd2 , 0 v e1 , v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 2.0 v logic low input threshold v il , v el 0.8 v v dd1 , v dd2 ? 0.1 5.0 v i ox = ?20 a, v ix = v ixh logic high output voltages v oah , v obh , v och , v odh v dd1 , v dd2 ? 0.4 4.8 v i ox = ?4 ma, v ix = v ixh 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl logic low output voltages v oal , v obl , v ocl , v odl 0.2 0.4 v i ox = 4 ma, v ix = v ixl
ADUM3400/adum3401/adum3402 rev. 0 | page 4 of 24 parameter symbol min typ max unit test conditions switching specifications adum340xarw minimum pulse width 3 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 4 1 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 50 65 100 ns c l = 15 pf, cmos signal levels pulse-width distortion, |t plh ? t phl | 5 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 7 t pskcd/od 50 ns c l = 15 pf, cmos signal levels adum340xbrw minimum pulse width 3 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 4 10 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 32 50 ns c l = 15 pf, cmos signal levels pulse-width distortion, |t plh ? t phl | 5 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 15 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 6 ns c l = 15 pf, cmos signal levels adum340xcrw minimum pulse width 3 pw 8.3 11.1 ns c l = 15 pf, cmos signal levels maximum data rate 4 90 120 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 18 27 32 ns c l = 15 pf, cmos signal levels pulse-width distortion, |t plh ? t phl | 5 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 10 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 2 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 5 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/low-to-high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance-to-high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output 8 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 8 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.2 mbps input dynamic supply current per channel 9 i ddi (d) 0.20 ma/mbps output dynamic supply current per channel 9 i ddo (d) 0.05 ma/mbps
ADUM3400/adum3401/adum3402 rev. 0 | page 5 of 24 1 all voltages are relative to their respective ground. 2 the supply current values for all four cha nnels are combined when running at identica l data rates. output supply current value s are specified with no output load present. the supply current associat ed with an individual channel op erating at a given data rate ca n be calculated as described in the power consumption section. see figure 8 through figure 10 for information on per-channel supply current as a functi on of data rate for unloaded and loaded conditions. see figure 11 through figure 15 for total v dd1 and v dd2 supply currents as a function of data rate for ADUM3400/adum3 401/adum3402 channel configurations. 3 the minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 4 the maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 5 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 6 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposi ng-directional channe l-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 9 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see fig ure 8 through figure 10 for information on per-channel supply current for unloaded and loaded conditions. see the power consumption section for guidance on calculating the per-channel supply current for a given data rate.
ADUM3400/adum3401/adum3402 rev. 0 | page 6 of 24 electrical characteristics3 v operation 1 2.7 v v dd1 3.6 v, 2.7 v v dd2 3.6 v; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 3.0 v. table 2. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.31 0.49 ma output supply current per channel, quiescent i ddo (q) 0.19 0.27 ma ADUM3400, total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 1.6 2.1 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 0.7 1.2 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 4.8 7.1 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 1.8 2.3 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 37 54 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 11 15 ma 45 mhz logic signal freq. adum3401, total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 1.4 1.9 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 0.9 1.5 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 4.1 5.6 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 2.5 3.3 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 31 44 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 17 24 ma 45 mhz logic signal freq. adum3402, total supply current, four channels 2 dc to 2 mbps v dd1 or v dd2 supply current i dd1 (q) , i dd2 (q) 1.2 1.7 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 or v dd2 supply current i dd1 (10) , i dd2 (10) 3.3 4.4 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 or v dd2 supply current i dd1 (90) , i dd2 (90) 24 39 ma 45 mhz logic signal freq. for all models input currents i ia , i ib , i ic, i id , i e1 , i e2 ?10 +0.01 +10 a 0 v ia , v ib , v ic , v id v dd1 or v dd2 , 0 v e1 ,v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 1.6 v logic low input threshold v il , v el 0.4 v v dd1 , v dd2 ? 0.1 3.0 v i ox = ?20 a, v ix = v ixh logic high output voltages v oah , v obh , v och , v odh v dd1 , v dd2 ? 0.4 2.8 v i ox = ?4 ma, v ix = v ixh 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl logic low output voltages v oal , v obl , v ocl , v odl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum340xarw minimum pulse width 3 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 4 1 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 50 75 100 ns c l = 15 pf, cmos signal levels pulse-width distortion, |t plh ? t phl | 5 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 7 t pskcd/od 50 ns c l = 15 pf, cmos signal levels
ADUM3400/adum3401/adum3402 rev. 0 | page 7 of 24 parameter symbol min typ max unit test conditions adum340xbrw minimum pulse width 3 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 4 10 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 38 50 ns c l = 15 pf, cmos signal levels pulse-width distortion, |t plh ? t phl | 5 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 22 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 6 ns c l = 15 pf, cmos signal levels adum340xcrw minimum pulse width 3 pw 8.3 11.1 ns c l = 15 pf, cmos signal levels maximum data rate 4 90 120 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 34 45 ns c l = 15 pf, cmos signal levels pulse-width distortion, |t plh ? t phl | 5 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 16 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 2 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 5 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/low-to-high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance-to-high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 3 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output 8 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 8 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.1 mbps input dynamic supply current per channel 9 i ddi (d) 0.10 ma/mbps output dynamic supply current per channel 9 i ddo (d) 0.03 ma/mbps 1 all voltages are relative to their respective ground. 2 the supply current values for all four cha nnels are combined when running at identica l data rates. output supply current value s are specified with no output load present. the supply current associat ed with an individual channel op erating at a given data rate ca n be calculated as described in the power consumption section. see figure 8 through figure 10 for information on per-channel supply current as a functi on of data rate for unloaded and loaded conditions. see figure 11 through figure 15 for total v dd1 and v dd2 supply currents as a function of data rate for ADUM3400/adum3 401/adum3402 channel configurations. 3 the minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 4 the maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 5 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 6 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposi ng-directional channe l-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 9 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see fig ure 8 through figure 10 for information on per-channel supply current for unloaded and loaded conditions. see the power consumption section for guidance on calculating the per-channel supply current for a given data rate.
ADUM3400/adum3401/adum3402 rev. 0 | page 8 of 24 electrical characteristicsmixed 5 v/3 v or 3 v/5 v operation 1 5 v/3 v operation: 4.5 v v dd1 5.5 v, 2.7 v v dd2 3.6 v; 3 v/5 v operation: 2.7 v v dd1 3.6 v, 4.5 v v dd2 5.5 v; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifica tions are at t a = 25c; v dd1 = 3.0 v, v dd2 = 5 v or v dd1 = 5 v, v dd2 = 3.0 v. table 3. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 5 v/3 v operation 0.57 0.83 ma 3 v/5 v operation 0.31 0.49 ma output supply current per channel, quiescent i ddo (q) 5 v/3 v operation 0.29 0.27 ma 3 v/5 v operation 0.19 0.35 ma ADUM3400, total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 2.9 3.5 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 1.6 2.1 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 5 v/3 v operation 0.7 1.2 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 1.2 1.9 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 5 v/3 v operation 9.0 11.6 ma 5 mhz logic signal freq. 3 v/5 v operation 4.8 7.1 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 5 v/3 v operation 1.8 2.3 ma 5 mhz logic signal freq. 3 v/5 v operation 3.0 5.5 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 5 v/3 v operation 72 100 ma 45 mhz logic signal freq. 3 v/5 v operation 37 54 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 5 v/3 v operation 11 15 ma 45 mhz logic signal freq. 3 v/5 v operation 19 36 ma 45 mhz logic signal freq. adum3401, total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 2.5 3.2 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 1.4 1.9 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 5 v/3 v operation 0.9 1.5 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 1.6 2.4 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 5 v/3 v operation 7.4 10.6 ma 5 mhz logic signal freq. 3 v/5 v operation 4.1 5.6 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 5 v/3 v operation 2.5 3.3 ma 5 mhz logic signal freq. 3 v/5 v operation 4.4 6.5 ma 5 mhz logic signal freq.
ADUM3400/adum3401/adum3402 rev. 0 | page 9 of 24 parameter symbol min typ max unit test conditions 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 5 v/3 v operation 59 82 ma 45 mhz logic signal freq. 3 v/5 v operation 31 44 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 5 v/3 v operation 17 24 ma 45 mhz logic signal freq. 3 v/5 v operation 32 46 ma 45 mhz logic signal freq. adum3402, total supply current, four channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 2.0 2.8 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 1.2 1.7 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 5 v/3 v operation 1.2 1.7 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 2.0 2.8 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 5 v/3 v operation 6.0 7.5 ma 5 mhz logic signal freq. 3 v/5 v operation 3.3 4.4 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 5 v/3 v operation 3.3 4.4 ma 5 mhz logic signal freq. 3 v/5 v operation 6.0 7.5 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 5 v/3 v operation 46 62 ma 45 mhz logic signal freq. 3 v/5 v operation 24 39 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 5 v/3 v operation 24 39 ma 45 mhz logic signal freq. 3 v/5 v operation 46 62 ma 45 mhz logic signal freq. for all models input currents i ia , i ib , i ic , i id , i e1 , i e2 ?10 +0.01 +10 a 0 v ia ,v ib , v ic ,v id v dd1 or v dd2 , 0 v e1 ,v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 5 v/3 v operation 2.0 v 3 v/5 v operation 1.6 v logic low input threshold v il , v el 5 v/3 v operation 0.8 v 3 v/5 v operation 0.4 v v dd1 , v dd2 ? 0.1 v dd1 , v dd2 v i ox = ?20 a, v ix = v ixh logic high output voltages v oah , v obh , v och , v odh v dd1 , v dd2 ? 0.4 v dd1 , v dd2 ? 0.2 v i ox = ?4 ma, v ix = v ixh 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl logic low output voltages v oal, v obl, v ocl , v odl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum340xarw minimum pulse width 3 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 4 1 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 50 70 100 ns c l = 15 pf, cmos signal levels pulse-width distortion, |t plh ? t phl | 5 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 7 t pskcd/od 50 ns c l = 15 pf, cmos signal levels
ADUM3400/adum3401/adum3402 rev. 0 | page 10 of 24 parameter symbol min typ max unit test conditions adum340xbrw minimum pulse width 3 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 4 10 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 15 35 50 ns c l = 15 pf, cmos signal levels pulse-width distortion, |t plh ? t phl | 5 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 22 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 6 ns c l = 15 pf, cmos signal levels adum340xcrw minimum pulse width 3 pw 8.3 11.1 ns maximum data rate 4 90 120 mbps c l = 15 pf, cmos signal levels c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 20 30 40 ns c l = 15 pf, cmos signal levels pulse-width distortion, |t plh ? t phl | 5 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 14 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 7 t pskcd 2 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 7 t pskod 5 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/low-to-high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance-to-high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f c l = 15 pf, cmos signal levels 5 v/3 v operation 3.0 ns 3 v/5 v operation 2.5 ns common-mode transient immunity at logic high output 8 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 8 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 5 v/3 v operation 1.2 mbps 3 v/5 v operation 1.1 mbps input dynamic supply current per channel 9 i ddi (d) 5 v/3 v operation 0.20 ma/mbps 3 v/5 v operation 0.10 ma/mbps output dynamic supply current per channel 9 i ddo (d) 5 v/3 v operation 0.03 ma/mbps 3 v/5 v operation 0.05 ma/mbps
ADUM3400/adum3401/adum3402 rev. 0 | page 11 of 24 1 all voltages are relative to their respective ground. 2 the supply current values for all four cha nnels are combined when running at identica l data rates. output supply current value s are specified with no output load present. the supply current associat ed with an individual channel op erating at a given data rate ca n be calculated as described in the power consumption section. see figure 8 through figure 10 for information on per-channel supply current as a functi on of data rate for unloaded and loaded conditions. see figure 11 through figure 15 for total v dd1 and v dd2 supply currents as a function of data rate for ADUM3400/adum3 401/adum3402 channel configurations. 3 the minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 4 the maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 5 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 6 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposi ng-directional channe l-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 9 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see fig ure 8 through figure 10 for information on per-channel supply current for unloaded and loaded conditions. see the power consumption section for guidance on calculating the per-channel supply current for a given data rate.
ADUM3400/adum3401/adum3402 rev. 0 | page 12 of 24 package characteristics table 4. parameter symbol min typ max unit test conditions resistance (input to output) 1 r i-o 10 12 capacitance (input to output) 1 c i-o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction-to-case thermal resistance, side 1 jci 33 c/w ic junction-to-case thermal resistance, side 2 jco 28 c/w thermocouple located at center of package underside 1 device considered a 2-terminal device; pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, and pin 8 shorted together and pin 9, pin 10, pin 11, pin 12, pin 13, pin 14, pin 15, and pin 16 shorted together. 2 input capacitance is from any input data pin to ground. regulatory information the adum340x is approved by the organizations listed in tabl e 5 . table 5. ul 1 csa vde 2 recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din en 60747-5-2 (vde 0884 part 2): 2003-01 2 double/reinforced insulation, 2500 v rms isolation voltage reinforced insulation per csa 60950-1-03 and iec 60950-1, 400 v rms maximum working voltage basic insulation, 560 v peak complies with din en 60747-5-2 (vde 0884 part 2): 2003-01, din en 60950 (vde 0805): 2001-12; en 60950: 2000 reinforced insulation, 560 v peak file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul1577, each adum340x is proof tested by a pplying an insulation test voltage 3000 v rms for 1 sec (current leakage detection limit = 5 a). 2 in accordance with din en 60747-5- 2, each adum340x is proof tested by applying an insulation te st voltage 1050 v peak for 1 s ec (partial discharge detection limit = 5 pc). the * marking branded on the comp onent designates din en 60747-5-2 approval. insulation and safety-related specifications table 6. parameter symbol value unit conditions rated dielectric insulation voltage 2500 v rms 1-minute duration minimum external air gap (clearance) l(i01) 7.7 min mm measured from input termin als to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 8.1 min mm measured from input termin als to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1)
ADUM3400/adum3401/adum3402 rev. 0 | page 13 of 24 din en 60747-5-2 (vde 0884 part 2) insulation characteristics table 7. description symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i-iv for rated mains voltage 300 v rms i-iii for rated mains voltage 400 v rms i-ii climatic classification 40/105/21 pollution degree (din vde 0110, table 1) 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage, method b1 v pr 1050 v peak v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc input-to-output test voltage, method a v pr after environmental tests subgroup 1 896 v peak v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc after input and/or safety test subgroup 2/3 672 v peak v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc highest allowable overvoltage (transient overvoltage, t tr = 10 sec) v tr 4000 v peak safety-limiting values (maximum value allowed in the event of a failure; also see figure 4 ) case temperature t s 150 c side 1 current i s1 265 ma side 2 current i s2 335 ma insulation resistance at t s , v io = 500 v r s >10 9 these isolators are suitable for basic electrical isolation only within the safety limit data. maintenance of the safety data i s ensured by protective circuits. the * marking on packages denotes din en 60747-5-2 approval. case temperature (c) safety-limiting current (ma) 0 0 350 300 250 200 150 100 50 50 100 150 200 side #1 side #2 0 5983-004 figure 4. thermal derating curve, dependence of safety-limiting values with case temperature per din en 60747-5-2 recommended operat ing conditions table 8. parameter symbol min max unit operating temperature t a ?40 +105 c supply voltages 1 v dd1 , v dd 2 2.7 5.5 v input signal rise and fall times 1.0 ms 1 all voltages are relative to their respective ground. see the dc correctness and magnetic field immunity sectio n for information on immunity to external magnetic fields.
ADUM3400/adum3401/adum3402 rev. 0 | page 14 of 24 absolute maximum ratings ambient temperature = 25c, unless otherwise noted. table 9. parameter symbol min max unit storage temperature t st ?65 +150 c ambient operating temperature t a ?40 +105 c supply voltages 1 v dd1 , v dd2 ?0.5 +7.0 v input voltage 1 , 2 v ia , v ib , v ic , v id , v e1 ,v e2 ?0.5 v ddi + 0.5 v output voltage 1 , 2 v oa , v ob , v oc , v od ?0.5 v ddo + 0.5 v average output current per pin 3 side 1 i o1 ?18 +18 ma side 2 i o2 ?22 +22 ma common-mode transients 4 cm h , cm l ?100 +100 kv/s 1 all voltages are relative to their respective ground. 2 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. see the pc board layout section. 3 see figure 4 for maximum rated current values for various temperatures. 4 refers to common-mode transients across the insulation barrier. common-mode transients exceeding the absolute maximum ratings can cause latch-up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly; functional operation of the device at these or any other conditions above those indicated in the operational section of this sp ecification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. table 10. truth table (positive logic) v ix input 1 v ex input 2 v ddi state 1 v ddo state 1 v ox output 1 notes h h or nc powered powered h l h or nc powered powered l x l powered powered z x h or nc unpowered powered h outputs retur n to the input state within 1 s of v ddi power restoration. x l unpowered powered z x x powered unpowered indeterminate outputs return to the input state within 1 s of v ddo power restoration if v ex state is h or nc. outputs return to high impedance state within 8 ns of v ddo power restoration if v ex state is l. 1 v ix and v ox refer to the input and output signals of a given channel (a, b, c, or d). v ex refers to the output enable signal on the same side as the v ox outputs. v ddi and v ddo refer to the supply voltages on the input and output sides of the given channel, respectively. 2 in noisy environments, connecting v ex to an external logic hi gh or low is recommended.
ADUM3400/adum3401/adum3402 rev. 0 | page 15 of 24 pin configurations and function descriptions v dd1 1 *gnd 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v ic 5 v oc 12 v id 6 v od 11 nc 7 v e2 10 *gnd 1 8 gnd 2 * 9 nc = no connect ADUM3400 top view (not to scale) 0 5983-005 figure 5. ADUM3400 pin configuration * pin 2 and pin 8 are internally connected and connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected and connecting both to gnd 2 is recommended. in noisy environments, connecting output enables (pin 7 for adum3401/adum3402 and pin 10 for all models) to an external logic high or low is recommended. table 11. ADUM3400 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2, 8 gnd 1 ground 1. ground reference for isolator side 1. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v id logic input d. 7 nc no connect. 9, 15 gnd 2 ground 2. ground reference for isolator side 2. 10 v e2 output enable 2. active high logic input. v oa , v ob , v oc , and v od outputs are enabled when v e2 is high or disconnected. v oa , v ob , v oc , and v od outputs are disabled when v e2 is low. in noisy environments, connecting v e2 to an external logic high or low is recommended. 11 v od logic output d. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 16 v dd2 supply voltage for isolator side 2, 2.7 v to 5.5 v.
ADUM3400/adum3401/adum3402 rev. 0 | page 16 of 24 v dd1 1 * gnd 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v ic 5 v oc 12 v od 6 v id 11 v e1 7 v e2 10 * gnd 1 8 gnd 2 * 9 nc = no connect adum3401 top view (not to scale) 0 5983-006 figure 6. adum3401 pin configuration * pin 2 and pin 8 are internally connected and connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected and connecting both to gnd 2 is recommended. in noisy environments, connecting output enables (pin 7 for adum3401/adum3402 and pin 10 for all models) to an external logic high or low is recommended. table 12. adum3401 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2, 8 gnd 1 ground 1. ground reference for isolator side 1. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v od logic output d. 7 v e1 output enable 1. active high logic input. v od output is enabled when v e1 is high or disconnected. v od is disabled when v e1 is low. in noisy environments, connecting v e1 to an external logic high or low is recommended. 9, 15 gnd 2 ground 2. ground reference for isolator side 2. 10 v e2 output enable 2. active high logic input. v oa , v ob , and v oc outputs are enabled when v e2 is high or disconnected. v oa , v ob , and v oc outputs are disabled when v e2 is low. in noisy environments, connecting v e2 to an external logic high or low is recommended. 11 v id logic input d. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 16 v dd2 supply voltage for isolator side 1, 2.7 v to 5.5 v.
ADUM3400/adum3401/adum3402 rev. 0 | page 17 of 24 v dd1 1 * gnd 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v oc 5 v ic 12 v od 6 v id 11 v e1 7 v e2 10 * gnd 1 8 gnd 2 * 9 nc = no connect adum3402 top view (not to scale) 0 5983-007 figure 7. adum3402 pin configuration * pin 2 and pin 8 are internally connected and connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected and connecting both to gnd 2 is recommended. in noisy environments, connecting output enables (pin 7 for adum3401/adum3402 and pin 10 for all models) to an external logic high or low is recommended. table 13. adum3402 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2, 8 gnd 1 ground 1. ground reference for isolator side 1. 3 v ia logic input a. 4 v ib logic input b. 5 v oc logic output c. 6 v od logic output d. 7 v e1 output enable 1. active high logic input. v oc and v od outputs are enabled when v e1 is high or disconnected. v oc and v od outputs are disabled when v e1 is low. in noisy environments, connecting v e1 to an external logic high or low is recommended. 9, 15 gnd 2 ground 2. ground reference for isolator side 2. 10 v e2 output enable 2. active high logic input. v oa and v ob outputs are enabled when v e2 is high or disconnected. v oa and v ob outputs are disabled when v e2 is low. in noisy environments, connecting v e2 to an external logic high or low is recommended. 11 v id logic input d. 12 v ic logic input c. 13 v ob logic output b. 14 v oa logic output a. 16 v dd2 supply voltage for isolator side 2, 2.7 v to 5.5 v.
ADUM3400/adum3401/adum3402 rev. 0 | page 18 of 24 typical performance characteristics data rate (mbps) current/channel (ma) 0 0 20 40 20 60 80 100 5v 3v 05983-008 15 10 5 figure 8. typical input supply current per channel vs. data rate (no load) data rate (mbps) current/channel (ma) 0 0 20 40 20 60 80 100 5v 3v 05983-009 15 10 5 figure 9. typical output supply current per channel vs. data rate (no load) data rate (mbps) current/channel (ma) 0 0 20 40 20 60 80 100 5v 3v 05983-010 15 10 5 figure 10. typical output supply current per channel vs. data rate (15 pf output load) data rate (mbps) current (ma) 0 0 80 40 20 60 80 100 5v 3v 05983-011 60 40 20 figure 11. typical ADUM3400 v dd1 supply current vs. data rate for 5 v and 3 v operation data rate (mbps) current (ma) 0 0 80 40 20 60 80 100 5v 3v 05983-012 60 40 20 figure 12. typical ADUM3400 v dd2 supply current vs. data rate for 5 v and 3 v operation data rate (mbps) current (ma) 0 0 80 40 20 60 80 100 5v 3v 05983-013 60 40 20 figure 13. typical adum3401 v dd1 supply current vs. data rate for 5 v and 3 v operation
ADUM3400/adum3401/adum3402 rev. 0 | page 19 of 24 data rate (mbps) current (ma) 0 0 80 40 20 60 80 100 5v 3v 05983-014 60 40 20 figure 14. typical adum3401 v dd2 supply current vs. data rate for 5 v and 3 v operation data rate (mbps) current (ma) 0 0 80 40 20 60 80 100 5v 3v 05983-015 60 40 20 figure 15. typical adum3402 v dd1 or v dd2 supply current vs. data rate for 5 v and 3 v operation temperature (c) propagation delay (ns) ?50 ?25 25 30 35 40 05 0 7 5 25 100 3v 5v 0 5983-016 figure 16. propagation delay vs. temperature, c grade
ADUM3400/adum3401/adum3402 rev. 0 | page 20 of 24 application information pc board layout the adum340x digital isolator requires no external interface circuitry for the logic interfaces. power supply bypassing is strongly recommended at the input and output supply pins (see figure 17 ). bypass capacitors are most conveniently connected between pin 1 and pin 2 for v dd1 and between pin 15 and pin 16 for v dd2 . the capacitor value should be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. bypassing between pin 1 and pin 8 and between pin 9 and pin 16 should also be considered unless the ground pair on each package side is connected close to the package. v dd1 gnd 1 v ia v ib v ic/oc v id/od v e1 gnd 1 v dd2 gnd 2 v oa v ob v oc/ic v od/id v e2 gnd 2 05983-017 figure 17. recommended printed circuit board layout in applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. failure to ensure this could cause voltage differentials between pins exceeding the devices absolute maximum ratings , thereby leading to latch-up or permanent damage. system-level esd considerations and enhancements system-level esd reliability (for example, per iec 61000-4-x) is highly dependent on system design which varies widely by application. the adum340x incorporate many enhancements to make esd reliability less dependent on system design. the enhancements include: ? esd protection cells added to all input/output interfaces. ? key metal trace resistances reduced using wider geometry and paralleling of lines with vias. ? the scr effect inherent in cmos devices minimized by use of guarding and isolation technique between pmos and nmos devices. ? areas of high electric field concentration eliminated using 45 corners on metal traces. ? supply pin overvoltage prevented with larger esd clamps between each supply pin and its respective ground. while the adum340x improve system-level esd reliability, they are no substitute for a robust system-level design. see application note an-793 esd/latch-up considerations with i coupler isolation products for detailed recommendations on board layout and system-level design. propagation delay-related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. the propagation delay to a logic low output can differ from the propagation delay to a logic high. input ( v ix ) output (v ox ) t plh t phl 50% 50% 05983-018 figure 18. propagation delay parameters pulse-width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signals timing is preserved. channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single adum340x component. propagation delay skew refers to the maximum amount the propagation delay differs between multiple adum340x components operating under the same conditions. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than 2 s, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses of more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see table 10 ) by the watchdog timer circuit. the limitation on the adum340xs magnetic field immunity is set by the condition in which induced voltage in the transformers receiving coil is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the 3 v operating condition of the adum340x is examined because it represents the most susceptible mode of operation.
ADUM3400/adum3401/adum3402 rev. 0 | page 21 of 24 the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, thus establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d /dt ) r n 2 ; n = 1, 2, , n where: is magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil in the adum340x and an imposed requirement that the induced voltage be at most 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 19 . magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 05983-019 figure 19. maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 v to 0.75 vstill well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the adum340x transformers. figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. as shown, the adum340x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. for the 1 mhz example noted, one would have to place a 0.5 ka current 5 mm away from the adum340x to affect the components operation. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 0 5983-020 figure 20. maximum allowable current for various current-to-adum340x spacings note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. care should be taken in the layout of such traces to avoid this possibility.
ADUM3400/adum3401/adum3402 rev. 0 | page 22 of 24 power consumption the supply current at a given channel of the adum340x isolator is a function of the supply voltage, the channels data rate, and the channels output load. for each input channel, the supply current is given by i ddi = i ddi ( q ) f 0.5 f r i ddi = i ddi (d) (2 f ? f r ) + i ddi ( q ) f > 0.5 f r for each output channel, the supply current is given by i ddo = i ddo ( q ) f 0.5 f r i ddo = ( i ddo ( d ) + (0.5 10 ?3 ) c l v ddo ) (2 f ? f r ) + i ddo ( q ) f > 0.5 f r where: i ddi (d) , i ddo (d) are the input and output dynamic supply currents per channel (ma/mbps). c l is the output load capacitance (pf). v ddo is the output supply voltage (v). f is the input logic signal frequency (mhz); it is half of the input data rate expressed in units of mbps. f r is the input stage refresh rate (mbps). i ddi (q) , i ddo (q) are the specified input and output quiescent supply currents (ma). to calculate the total i dd1 and i dd2 supply current, the supply currents for each input and output channel corresponding to v dd1 and v dd2 are calculated and totaled. figure 8 provides per- channel input supply current as a function of data rate. figure 9 and figure 10 provide per-channel supply output current as a function of data rate for an unloaded output condition and for a 15 pf output condition, respectively. figure 11 through figure 15 provide total v dd1 and v dd2 supply current as a function of data rate for ADUM3400/adum3401/adum3402 channel configurations.
ADUM3400/adum3401/adum3402 rev. 0 | page 23 of 24 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 16 9 8 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 10.50 (0.4134) 10.10 (0.3976) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) coplanarity 0.10 figure 21. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters and (inches) ordering guide model temperature range (c) number of inputs, v dd1 side number of inputs, v dd2 side maximum data rate (mbps) maximum propagation delay, 5 v (ns) maximum pulse-width distortion (ns) package option 1 ADUM3400arwz 2 , 3 ?40 to +105 4 0 1 100 40 rw-16 ADUM3400brwz 2 , 3 ?40 to +105 4 0 10 50 3 rw-16 ADUM3400crwz 2 , 3 ?40 to +105 4 0 90 32 2 rw-16 adum3401arwz 2 , 3 ?40 to +105 3 1 1 100 40 rw-16 adum3401brwz 2 , 3 ?40 to +105 3 1 10 50 3 rw-16 adum3401crwz 2 , 3 ?40 to +105 3 1 90 32 2 rw-16 adum3402arwz 2 , 3 ?40 to +105 2 2 1 100 40 rw-16 adum3402brwz 2 , 3 ?40 to +105 2 2 10 50 3 rw-16 adum3402crwz 2 , 3 ?40 to +105 2 2 90 32 2 rw-16 1 rw-16 = 16-lead wide body soic. 2 tape and reel are available. the addition of an -rl suffix de signates a 13 (1,000 unit s) tape and r eel option. 3 z = pb-free part.
ADUM3400/adum3401/adum3402 rev. 0 | page 24 of 24 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d0598 5-0-3/06(0)

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